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Dataflow-Architecture Co-Design for 2.5D DNN Accelerators using Wireless Network-on-Package
[FPGA'22] HeteroFlow: An Accelerator Programming Model with Decoupled Data Placement for FPGAs
Heterogeneous Dataflow Accelerators for Multi-DNN Workloads
Dataflow in ASIC hardware accelerators
A flexible dataflow CNN accelerator on FPGA
Dataflow Hardware Acceleration of DNNs with High-Level Synthesis | Guest Lecture at Yale University
Guest lecture: Hardware Accelerator for DNN part 1
Procrustes: A Dataflow and Accelerator for Sparse Deep Neural Network Training
[LATTE 23] #3: Designing a Dataflow Hardware Accelerator with an Abstract Machine
[FPGA 2022] Towards Agile DNN Accelerator Design Using Incremental Synthesis on FPGAs
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Last Updated: September 29, 2026
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A huge amount has been published about deep neural network Deep neural networks (DNNs) can be efficiently executed on Tutorial Website: accelergy.mit.edu/sparse_tutorial.html Information about accessibility can be found at ... Robert Guirado presents the paper " Presented by Shaojie Xiang at FPGA2022, online. Abstract: To achieve high performance with FPGA-equipped heterogeneous ... DL Compiler Study Paper: Heterogeneous Presenter Shreyas Ravishankar AI Hardware Researcher AI Lab. CCGrid 2023 research poster presentation Title: A flexible Talk for the ASPLOS 2023 LATTE Workshop on "Designing a Qingcheng Xiao, Peking University Yun Liang, Peking University Hardware-software co-design is the new trend for deep neural ...